JV
João V.Verified purchase
Your cart is empty
Add prompt packs to continue
Copy, paste and use them in your favorite AI:
Just $0.08 per prompt · one-time payment
100 resources included
This exclusive collection represents the cutting edge in support tools for modern mechatronic engineering. Meticulously designed by content strategy experts, each prompt acts as a productivity catalyst ranging from precision mechanics to integrating advanced artificial intelligence into complex industrial environments. By implementing these resources, organizations achieve a significant reduction in response times to critical failures and a substantial improvement in the quality of the architecture of embedded systems and industrial control. It is the definitive ecosystem to transform technical knowledge into tangible, scalable results aligned with international industry 4.0 standards.
He acts as a Senior Automation Engineer with a specialty in PLC programming under the IEC 61131-3 standard. Your task is to design a robust and highly efficient software architecture for 'Remote Digital Input Mapping' in a distributed system using [Make and Model of PLC, e.g. Siemens S7-1500 / Allen-Bradley ControlLogix]. The main objective is to completely decouple the physical addresses from the process variables (I/O Mapping) to facilitate the maintenance, readability and scalability of the control system in a [Industry Type] plant. Start by defining a user data structure (UDT) that not only contains the boolean state of the input, but also diagnostic-critical metadata. This structure, called 'ST_DigitalInput', must include: the current logical state, a signal quality bit, a noise filtering timer (Debounce Timer), an activation counter for preventive maintenance and a text string for the description of the associated sensor. This approach allows each digital input to be treated as a smart object within the programming environment. Develop a specific mapping routine in [Programming Language, e.g. SCL or Structured Text] that runs in a cyclic organization block (OB) with an appropriate priority. The logic must read the memory area of the decentralized periphery connected via [Communication Protocol, e.g. PROFINET / EtherNet/IP / Modbus TCP] and transfer the data to the previously defined Structure Array. It is essential to include software-configurable 'Anti-Bounce' (Debouncing) logic for each input, avoiding false triggering caused by electrical noise in long cables. Implements an advanced communication failure management system. If the connection with the remote node [Node Identifier, e.g. ET200SP / Point I/O] is interrupted, the mapping system must detect the loss of the 'Heartbeat' and force all critical inputs to a fail-safe state defined by [Safety Settings, e.g. Safe State OFF / Freeze Last Value]. In addition, it generates a status word (Status Word) that summarizes the hardware errors of the entire remote rack to be sent directly to the HMI/SCADA system. Finally, optimize the code to be scalable and modular. The user should be able to expand the number of entries from [Initial Quantity] to [Maximum Quantity] simply by modifying the upper limit constant of the Array, without needing to rewrite the processing logic. It provides the source code commented in detail in Spanish, following the CamelCase or Snake_Case nomenclature standards depending on the preference of the selected platform, and ensures that the computational load (CPU Scan Time) remains within the optimal limits for high-speed processes. If any key information needed to fill the bracketed fields is missing, ask me the necessary questions before answering.
Instant access after purchase from your dashboard. Just copy and paste into your AI.
ChatGPT, Claude, Gemini, DeepSeek, Grok, Qwen and any AI chat.
Yes. Every prompt includes bracketed fields where you insert your own information, context and specifics, so they fit your situation, country or industry.
Yes. Above you can read full sample prompts, exactly as you'll receive them, to check the quality before paying.
Yes. Pay once and they're yours forever, updates included.
Acts as a Senior Embedded Systems Engineer and Firmware Developer with extensive experience in real-time architectures (RTOS) and critical hardware control. Your objective is to design a robust and efficient architecture for the 'Handling of priority external interruptions' within a system based on the microcontroller [Microcontroller_Model], which is part of a smart device oriented to [Device_Specific_Application]. The solution must guarantee a deterministic response latency to critical events triggered by the hardware, such as signals from [Sensor_or_Critical_Peripheral] or emergency stop buttons. The design should start with detailed configuration of the interrupt controller (NVIC on ARM or similar), establishing a clear hierarchy of priorities and sub-priorities to avoid collisions and ensure that safety events have absolute precedence over communication tasks such as [Secondary_Communication_Protocol]. You must document the configuration of the control registers, the selection of the trigger edge (rising, falling or both edge) and the implementation of filtering or 'debouncing' mechanisms for noisy signals, specifying whether it will be done using external hardware or optimized firmware logic. Develop the source code in C language following the MISRA C standard to ensure the reliability of the system. Interrupt Service (ISR) functions must be extremely compact and efficient, avoiding any blocking or long input/output operations. Implements a 'Deferred Interrupt Processing' strategy using [RTOS_Synchronization_Mechanism] to move heavy processing to lower priority tasks, thus maintaining system availability for new high-frequency interrupts. It includes handling shared variables by using 'volatile' qualifiers and protecting critical sections by temporarily disabling interrupts or using binary semaphores. Finally, it provides a power impact analysis and debugging guide to identify possible cases of priority inversion or stack overflow caused by nested interrupts. The final result should include commented code snippets, a logical schematic of the interrupt hierarchy, and a custom interrupt vector table for the proposed scenario. If any key information needed to fill the bracketed fields is missing, ask me the necessary questions before answering.
He acts as a Senior Firmware and Hardware Engineer with specialization in Ultra-Low Power Design for mission-critical embedded systems in the field of Mechatronics Engineering. Your goal is to design an end-to-end architecture that minimizes current consumption (microamps/nanoamps) for a microcontroller-based smart device [MCU model, e.g. STM32U5, ESP32-S3, nRF52840] operating via [Power Supply, e.g. Li-Po Battery 3.7V, Energy Harvest]. The system must integrate sensors of type [Type of sensors] and a communication module [Protocol, e.g. LoRaWAN, BLE, NB-IoT]. Develop a power management strategy at the firmware level detailing the implementation of low power modes (Sleep, Deep Sleep, Hibernate). You should explain how to configure the interrupt handler to wake the system only by critical external events or ultra-precise hardware timers. It includes the logic for 'Clock Gating' of unused peripherals and the reduction of the system clock frequency (DVS - Dynamic Voltage Scaling) during processes that do not require high computing capacity. Ensure that the communication protocol stack is managed by a finite state machine that minimizes the radio's 'Duty Cycle' time. At the hardware level, it analyzes and proposes improvements in the design of the voltage regulation stage, comparing the efficiency of Buck-Boost converters versus ultra-low quiescent current (Iq) LDOs for this specific use case. Evaluate the impact of leakage currents on the GPIO pins and design a galvanic isolation or load switching scheme to physically disconnect high-power sensors and peripherals when the system is in deep sleep state. Provides estimated battery life calculations based on a usage profile of [Sample Rate] and [Transmit Rate]. Finally, generate a power profiling guide using hardware tools (Power Profilers) and code debugging techniques to identify unexpected current spikes. The answer should include code snippets in C/C++ using low-level abstractions or RTOS (specify whether FreeRTOS, Zephyr, or Bare Metal is preferred) for manipulating power registers and managing retained RAM during deep sleep mode. If any key information needed to fill the bracketed fields is missing, ask me the necessary questions before answering.
It's a master instruction, optimized for AI.
Prompt
your instruction
AI
Result
Based on 10 reviews
It does the job, though I expected a bit more. Some prompts are great and others more generic. Could be better but useful.
Exceeded my expectations. The quality of the answers I get improved a lot. Totally recommend them.
I was impressed by the quality. The prompts are really well thought out and the effort shows. One hundred percent recommended.
It does the job, though I expected a bit more. They work as a starting point. Acceptable.
I was impressed by the quality. They're easy to adapt to my case by just changing the fields. I'll buy again without hesitation.
It's fine, nothing more. Some prompts are great and others more generic. Could be better but useful.
Good value for money. The prompts are useful and practical. Came close to a five.
I was impressed by the quality. The index is organized and I find what I need instantly. One hundred percent recommended.
I didn't expect them to be this complete. The index is organized and I find what I need instantly. One hundred percent recommended.
Exactly what I was looking for. The prompts are really well thought out and the effort shows. I'll buy again without hesitation.